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2-101 features ? 16 bit wide data bus i/o ? 16 bit address bus ? microprocessor interface ? 2048 x 16 bit wide memory sram ? interfaces with mitels mt9085b to form larger switch mitoses ? variable clock and frame rates applications ? small and medium digital switch matrices ? telephony equipment - pbx, co equipment, digital cross connect, digital local loop ? datacom equipment - access concentrators, lan/wan gateways description the MT9080B is a ?exible memory module suitable for use as a basic building block in the construction of customized digital switching matrices. it can be con?gured as either a data memory or a connection memory, and is designed to interface with mitels mt9085b. interface to the device is via 16 bit wide data and address busses. the MT9080B can operate with variable clock rates up to 16.7 mhz. figure 1 - functional block diagram d0i/d15i a0-a15 me 16 16 16 16 address mux 11 bit counter counter reset 2048 x 16 static memory control interface wr enable precharge d0o/ cd 11 crc fp ck ode ds cs r/ wmxmy mz dta d15o ordering information MT9080Bp 84 pin plcc -40 c to 70 c ds5140 issue 4 march 1999 MT9080B smx - switch matrix module cmos
MT9080B cmos 2-102 figure 2 - pin connections pin description pin # name description 1v ss ground. 2-5 d0i-d3i input/microport data bus. this is part of a 16 bit data bus. the data bus is bidirectional in connect memory mode where it is typically interfaced to a microprocessor. in all other modes the data bus is an input. data to be switched through the device is clocked in at this port. 6v ss ground. 7-10 d4i-d7i input/microport data bus. see description for pins 2-5 above. 11 v ss ground. 12-15 d8i-d11i input/microport data bus. see description for pins 2-5 above. 16 v ss ground. 17-20 d12i-d15i input/microport data bus. see description for pins 2-5 above. 21 v ss ground. 22 ck clock. master clock input which is used to clock data into and out of the device. it also clocks the internal 11 bit counter. 23 v dd +5v supply input. 24 v ss ground. 25,26 ic internal connection. should be tied to v ss for normal operation. 27 fp frame pulse. an active low signal that serves as a synchronous clear for the internal 11 bit counter in all modes except shift register mode. the counter is cleared on a rising edge of ck. in the shift register mode, fp serves to align channel boundaries. 74 56 58 60 62 64 68 70 72 66 12 28 26 24 22 18 16 14 20 vss 32 30 54 10 8 6 4 2 84 82 80 78 76 34 36 38 40 42 44 46 48 50 52 nc ode me mx my mz nc ic ic vss vdd nc a0 a1 a2 a3 a4 a5 a6 a7 vss d7o d6o d5o d4o vss d3o d2o d1o d0o vss cd a14 a13 a12 a11 a10 a9 a8 d8i d9i d10i d11i d13i d14i d15i vss vss ic ck vdd ic fp cs ds r/ w dt a nc vss d7i d6i d5i d4i vss d3i d2i d1i vss vdd d15o d14o d13o d12o vss d11o d10o d9o d8o d0i 84 pin plcc vdd a15 vss d12i
cmos MT9080B 2-103 28 cs chip select. active low input. selects the device for microport access in connect memory, data memory, external and shift register modes. tying cs high will disable output data drivers (d0-d15o) in all modes except connect memory and shift register modes. 29 ds data strobe. active low input. indicates to the smx that valid data is present on the microport data bus during a write operation or that the smx must output data on a read operation. in connect memory modes, a low level applied to this input during a write operation indicates to the smx that valid data is present on the microport data bus. during a read operation the low going signal indicates to the smx that it must output data on the microport data bus. in data memory and external modes, when ds is high, the output data bus d0o-d15o will be disabled. the input data bus d0i-d15i is not affected. the ds input has no effect on the input and output busses in counter or shift register modes. 30 r/ w read/write enable. data is written into the device when r/ w is low and read from it when it is high. this control input is disabled in data memory and shift register modes. it should be tied to v ss or v dd in these modes. in counter and external modes, the state of r/ w pin is clocked in with the rising edge of ck. the actual read or write operation will be implemented on the next rising clock edge. 31 dt a data transfer acknowledge. open drain output which is pulled low to acknowledge completion of microport data transfer. on a read of the smx, dt a low indicates that the smx has put valid data on the data bus. on a write, dt a low indicates that the smx has completed latching the data in. 32 nc no connection. 33 v ss ground. 34 nc no connection. 35 ode output data enable. control input which enables the output data bus. pulling this input low will place the data bus in a high impedance state. the level on this pin is latched by a rising edge of ck. the output drivers will be enabled or disabled with the rising edge in the next timeslot (see fig. 24 for applicable timing in different modes). 36 me message enable. when tied high the data latched in on the address bus is clocked out on d0o-d15o. when me is tied low, the contents of the addressed memory location will be output on the bus. the level on this pin is latched in with the rising edge of the clock. the actual mode change is implemented on the rising edge in the next timeslot. refer to figures 25 and 26 for more timing information. 37 mx mode x. one of three inputs which permit the selection of different operating modes for the device. refer to table 1 for description of various modes. 38 my mode y. see description for pin 37. 39 mz mode z. see description for pin 37. 40 nc no connection. 41, 42 ic internal connection. leave open for normal operation. 43 v ss ground. 44 v dd supply voltage. +5v. 45 nc no connection. pin description pin # name description
MT9080B cmos 2-104 46-61 a0-a15 address bus. these inputs have three different functions. inputs a0-a10 are used to address internal memory locations during read or write operations in all modes except shift register mode. in shift register mode, the levels latched in on a0-a10 program the delay through the device. when the me pin is tied high, the data latched in on a0-a15 is clocked out on to the data bus (d0o-d15o). 62 cd change detect. open drain output which is pulled low when a change in the memory contents from one frame to the next is detected by a cyclic redundancy check (crc). changes in memory contents resulting from microprocessor access do not cause cd to go low. the output is reset to its normal high impedance state when the ds input is strobed, while the device has been selected ( cs is low). 63 v dd supply voltage. +5v. 64 v ss ground. 65-68 d0o-d3o output data bus. these three state outputs are part of a 16 bit data bus which is used to clock out data from the device. data is clocked out with the rising edge of the clock. see figures 24 to 26 for timing information. the bus is actively driven when ode is tied high. it is disabled when ode is tied low. tying cs high will also disable the output data bus in all modes except connect memory and shift register modes. 69 v ss ground. 70-73 d4o-d7o output data bus. see description for pins 65-68. 74 v ss ground. 75-78 d8o-d11o output data bus. see description for pins 65-68. 79 v ss ground. 80-83 d12o-d15 o output data bus. see description for pins 65-68. 84 v dd supply voltage. +5v. pin description pin # name description
cmos MT9080B 2-105 functional description the smx is a ?exible memory module suitable for use in the construction of timeslot interchange circuits used in pcm voice or data switches. the device can be con?gured as a data memory or a connection memory. the smx has separate 16 bit input and output data busses. a 16 bit address bus and a full microprocessor interface is also provided. data is clocked into and out of the device with the signal applied at the ck (clock) input. depending on the mode of operation, the memory locations for the read or write operation can be addressed sequentially by the internal counter or randomly via the external address bus. a messaging sub-mode, which permits the data latched in on the address bus to be multiplexed on to the output data bus, is also available (see me pin description). the smx ensures integrity of the stored data by performing a cyclic redundancy check (crc) on a per frame basis. when a change in the memory contents is detected from one frame to the next, the change detect ( cd ) pin is pulled low. the output will be reset to its normal high impedance state when ds input is strobed while cs is low (i.e., while the device has been selected for microprocessor access). the cd output is not pulled low when the memory contents have been modi?ed by a processor access to the device. modes of operation the smx can be programmed to operate in one of eight modes as summarized in table 1. the different modes are used to realize speci?c switch implementations. for example, to implement a 1024 channel switch, two smxs are required. one is operated in data memory mode, while the second is operated in connect memory mode. a 2048 channel switch can be realized using three smxs. two of the devices are operated, alternatively, in counter and external modes, the third serves as the connection memory. a detailed description of the implementation is presented in the applications section of this data sheet. an outline of the device functionality in each mode is presented below. table 1. smx modes of operation data memor y mode-1 data memory mode-1 is designed for use in the construction of a 1024 channel switch matrix. data on the d0-d15 input bus is clocked into the smx and stored in memory locations addressed by the internal 11 bit counter. data is clocked out according to the addresses asserted on the address bus. the pin con?guration of the device in this mode is illustrated in figure 3 figure 3 - data memory modes 1 and 2 pinout the timing for the read and write operation is illustrated in figure 4. the ?rst half of each clock period is used for precharging the internal bus. data is latched in and out of the device with rising edge of the ck clock. correct operation of the device in this mode requires 2048 clock cycles in a single frame de?ned by the frame pulse. consequently, for switching of 64 kbit/s pcm voice channels, the clock frequency must be 16.384 mbit/s with a frame rate of 8 khz. the address supplied on the address bus is latched in with the ?rst positive clock edge in a channel timeslot. the contents of the memory location addressed will be clocked out on d0-d15o with the ?rst positive clock edge in the next timeslot (see figure 4). in data memory mode-1, the delay through the switch depends on the number of channel timeslots between the input channel and the output channel. if the time difference between the input channel and output channel is less than two channels, data clocked into the device in the current frame will be clocked out in the next frame. if the difference is greater than or equal to two channels, data will be clocked out in the same frame. this concept is further illustrated in figure 5. mode m x m y m z name abbr. 1 2 3 4 5 6 7 8 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 data memory - 1 data memory - 2 connect memory - 1 connect memory - 2 counter mode external mode shift register mode data memory - 3 dm-1 dm-2 cm-1 cm-2 cnt ext sr dm-3 data input data output 16 fp d0 i -d15 i cd a0-a15 me ode z y z d0 o -d15 o cs ds dta 16 mode ck from control interface
MT9080B cmos 2-106 figure 4 - data memory mode functional timing figure 5 - throughput delay in data memory mode-1 ck external address bus a0-a15 data output d0-d15o fp address generated by internal 11 bit counter data input d0-d15i ch x ch y ch z 1022 1023 0 1 2 1 0 1023 counter reset ch x ch y ch z pwp r - p = precharge r = read memory w = write memory data is clocked out of the memory location addressed by external address bus. the address is latched in with ck edge marked . data is clocked out with ck edge marked - . data is latched into the device with the last rising edge of ck in the timeslot (e.g., edge a in diagram). it is stored in the a? memory location address by the internal 11 bit counter with the next rising clock edge (edge ? in diagram). ck pw r - p 1 4 12345 2 3 p = precharge r = read memory w = write memory data on the input bus of the smx is latched into the device with last rising edge of the clock within a timeslot. it is data is clocked out of the memory location and latched onto the output data bus with first positive clock edge in the input data output timeslots written into the internal memory with the following positive edge. timeslot. switching channel 1 to channel 1 or channel 2 will result in one frame delay. note that channel 2 is clocked out by ck edge labelled while channel 1 is written into the memory with edge - . however, if channel 1 is switched to channel 3, there will be only one channel delay.
cmos MT9080B 2-107 this mode provides minimum delay through the smx for any switching con?guration. data memor y mode-2 data memory mode-2 is designed for use in constructing a 1024 by 1024 channel double buffered switch. this mode is similar in most respects to data memory mode-1. the double buffering is achieved by dividing the internal 2048 memory into two equal blocks. in a single frame, data is written into the ?rst block and read from the second. in the next frame, the data will be written into the second and read from the ?rst (see figure 6). frame sequence integrity of the data will be maintained for all switching con?gurations if the output frame is delayed by one channel with respect to the input frame. in this case, data clocked into the device during any of the channels in the current frame will be clocked out in the next frame. however, if the input and output frames are aligned, then data switched from any input channel to output channels 0 or 1 will be clocked out one frame after the next - consequently frame sequence integrity is not maintained for channels 0 or 1. frame sequence integrity will be maintained for data switched to any of the other output channels. (see smx/pac application note, msan-135, for more information.) it is possible to switch between data memory mode-1 and mode-2 on a per timeslot basis. data memor y mode-3 this mode is similar to data memory mode-1. however, there is no restriction on the minimum acceptable clock frequency or frame rate. in this mode, the size of the switching matrix depends on the clock and frame rates provided as per the following relationship: where s is the number of channels in the switching matrix f fp is the frame pulse frequency in hz, and f ck is the clock frequency in hz. the following table shows how the size of a switching matrix can be varied by selecting a suitable combination of clock and frame rates. it is not possible to switch between data memory mode-3 and other modes on per-timeslot basis. connect memor y mode -1 in connect memory mode-1, the input data bus is bidirectional. internal memory locations can be randomly accessed via the microprocessor bus. the pinout of the device in this mode is illustrated in figure 7. ck (mhz) fp (khz) number of channels in the switching matrix 16.384 16.384 16.384 12.288 12.288 8.192 8.192 4 8 16 4 8 4 8 2,048 1,024 512 1,536 768 1,024 512 s = f ck 2 x f fp figure 6 - data memory mode-2 functional timing ck data input data output frame 0 frame 1 frame 2 frame 1 frame 2 1023 0 1 1023 01 0 1 0 1 written to block 0 written to block 1 read from block 1 read from block 0 frame 0 written to block 1 read from block 0 1023 1023 note: no input and output channel alignment is implied in the example shown above. it is assumed that the frame pulse for the connection memory used to generate adresses for the read operation has a specific phase relationship with respect to the data memory frame pulse.
MT9080B cmos 2-108 figure 7 - connect memory modes pinout data is clocked out on d0 o -d15 o from memory locations addressed sequentially by the internal counter. this counter is incremented every second clock period and is reset with fp. the frequency of the clock signal used should be twice the data rate. a timing diagram showing the relationship between the data output and the clock signal is presented in figure. 8. with a clock rate of 16.384 mhz, the maximum number of addresses that can be generated in an 8 khz frame period is 1024. fig. 8 - connect memory mode-1 functional timing microprocessor access timing is shown in figures 28 and 29. during a microprocessor read cycle, ds low indicates to the smx that the processor is ready to receive data. the smx responds by pulling dt a low when there is valid data present on the bus. the processor latches the data in and sets ds high. the smx completes the bus cycle by disabling the dt a. ds should be kept low until after dt a is issued by the smx. cs, r/ w and the address lines should also be asserted for the duration of the access. a mpu write cycle is similar to the read cycle. data will be latched into the device approximately three clock (ck) cycles after ds goes low. when the device has latched the data in, it will pull dt a low. ds can subsequently be set high. connect memor y mode-2 connect memory mode-2 is designed speci?cally for 2048 channel switching applications. data is clocked out on d0 o -d15 o with every rising clock edge from memory locations addressed sequentially by the internal counter (see figure 9). this counter is incremented with each clock period and is reset with fp or when a count of 2047 is reached. fig. 9 - connect memory mode-2 functional timing the clock frequency should be 16.384 mhz for a connection memory designed to support a 2048 channel switch. microprocessor access is similar to connect memory mode-1. counter mode this mode is designed for 2048 channel switching applications. in the counter mode all read and write addresses are generated sequentially by the internal 11 bit counter. the 11 bit counter is incremented with each clock pulse. it will wrap around when it reaches a count of binary 2047 or when it is reset by fp. the active input/output pins in this mode are illustrated in figure 10. fig. 10 - counter mode pinout 16 ck d0-d15 16 ode me z y x mode cd dta cs ds r/ w a0-a15 d0 o -d15 o fp 0/1 1 0 microprocessor interface fp ck data out 1023 0 fp ck data output 2047 0 1 2 16 d0 i -d15 i ck fp d0 o -d15 o cs ode dta cd r/ wme xyz 16 all other inputs should be tied low 10 0
cmos MT9080B 2-109 the device can perform either a read or a write, depending on the level asserted at the r/ w pin. when r/ w is high, the contents of the memory addressed by the internal counter will be clocked out on to the output data bus. setting r/ w low will enable data on the input data bus to be written into the device. during a write operation, the output bus is actively driven by the data latched out in the previous read operation. data is clocked in or out of the device on the positive edge of the clock. see figure 11. figure 11 - counter mode functional timing external mode the external mode, which is designed for use in 2048 switching applications, permits random access to the memory both for input and output operations. the pinout for external mode is shown in fig. 12. the address asserted on the external address bus is used to specify the memory location to be accessed for the read or write operation. the level asserted on r/ w during a speci?c clock period determines whether the addressed memory is written to or read from. during a write operation, the output data bus is actively driven with data latched out in the previous read operation. data is clocked into or out of the device on the positive edges of the clock as shown in figure 13. shift register mode in this mode, data clocked into the smx is delayed by a number of clock cycles before being clocked out of the device. the delay introduced (in number of clock cycles) is equal to two times the binary value of the address latched into the device plus 2. for example, if the address asserted is hex 02, the delay through the switch is equal to six clock cycles. figure 12 - external mode pinout figure 13 - external mode functional timing maximum permissible delay is equal to 4096 clock cycles. the pertinent timing parameters are illustrated in figure 14. data is clocked in and out of the device with rising edge of the clock. the address is latched in with the negative edge of ds while the cs is low. ck fp internal counter data clocked out (r/ w high) data clocked in (r/ w low) 2047 0 1 2 3 012 2047 0 1 2 3 16 d0 i -d15 i ck fp d0 o -d15 o cs ds cd r/ w a0-a11 x y z 16 ode dta me 101 all other inputs should be tied low ck fp addr data in (r/ w low) data out (r/ w high) ch x ch y ch z xyz ch x ch y ch z
MT9080B cmos 2-110 figure 14 - shift register mode data input/output timing ch x ch y ch z ch x ch y ch z t d t d = (address x 2) + 2 clock cycles ck fp data in data out applications 1024 channel switch matrix a 1024 channel, non-blocking, timeslot interchange switch can be constructed using two smx devices (refer to figure 15). one smx is operated in the data memory mode, while the second device is operated in connect memory mode-1. data to be switched is clocked into the data memory via the 16 bit input data bus and stored sequentially in memory locations addressed by the internal 11 bit counter. the data is read out of the data memory (smx#1) according to the external address supplied by the connection memory (smx#2). the connection memory clocks out contents of the memory according to the addresses supplied by the internal counter. the clock applied at the ck input of both the devices has a frequency of 16.384 mhz. there are two clock periods in each channel timeslot (see figure 16). a framing signal ( fp) with a frequency of 8 khz is used to delineate frames with 1024 channels each. the fp input to the data memory is delayed by seven clock periods from the connection memory frame pulse. this phase delay synchronizes the internal counters of the two smxs such that the connection memory clocks out addresses one channel ahead of the affected timelsot. using the connections illustrated in figure 15, the data memory address and control functions can be mapped onto speci?c bits of the connect memory to form a 16 bit control word, as shown in figure 17. the 16 bit control word is written into the connection memory by the processor. subsequently, when the memory location is addressed by the internal counter, this word will be clocked out of the memory on to the data bus (d0 o -d15 o ). the output on the connect memory data bus (d0 o -d9 o ) is used to specify the data memory location to be read out during any particular timeslot. the connection memory is programmed in a manner that permits speci?c addresses to be output in certain timeslots. the data memory will clock out data from internal memory locations according to the address asserted on its address bus. as mentioned earlier, this address is latched into data memory with a positive edge of the clock. the contents of the appropriate addressed memory location will be clocked out of the device at the beginning of the next channel timeslot. connection memory bit 10 controls the level on the ode input. the ode pin is used to enable the output drivers of the data memory. the capability to selectively enable or disable the output drivers during speci?c channel timeslots is required when constructing larger switches using the 1024 channel switch as a building block. the message enable (me) input of the data memory is controlled by d11. setting this particular bit high will result in the data latched into the address bus being clocked out on to the data memory output bus. note that only 10 of the 16 address inputs are actually connected to the data bus of the connection memory. consequently, only 10 of the 16 data output bits on the data memory can be dynamically controlled through the connection memory. in other applications, all 16 of the address bits may be connected to the data output bus of the connection memory. the mode of operation of the data memory can be changed from data memory mode-1 to data memory mode-2 by setting or resetting d12 in the connection
cmos MT9080B 2-111 memory. the delay through the matrix can be optimized for speci?c applications by selectively enabling one of the two modes. data memory-1 (dm-1) is designed for voice switching applications where it is generally desirable to minimize delay through the switch. as mentioned earlier in the dm-1 description, the delay through the switch depends upon the difference between the input channel timeslot and the output channel timeslot. consecutive output channels switched from non-contiguous input channels will not always originate from the same input frame. for example, if channels 3, 6 and 8 are to be switched to channels 5, 6 and 7; output channel 5 will contain data input in the current frame, while channels 6 and 7 will contain data clocked in one frame earlier. data memory-2 (dm-2) is designed for data switching applications where concatenation of a number of channels is often necessary. data clocked out of the device will originate from the previous frame, regardless of the input/output time difference. there is one exception, when channel 1023 is switched to channel 0, the contents of channel 0 will not originate from the previous frame but rather from the frame before it. the capability to selectively change between dm-1 and dm-2 allows a single switch to handle both voice and data effectively. external bus drivers can be controlled with d13 of the connection memory data bus. this bit will be output along with the remaining bits one channel figure 15 - 1024 channel switch matrix parallel input data parallel output data 16 16 d0 i -d15 i d0 o -d15 o smx #1 dm-1/2 data memory a10-a15 r/ w cs ds fp ck a0-a9 ode me z y x mode 10 +5 external tristate control timing generator fp#1 ck fp#2 d0 o -d9 o d10 o d11 o d12 o d13 o x y z mode a11-a15 a10 cs ck fp cd d0-d15 r/ w dta ds a0-a9 smx #2 cm-1 connection memory 0 1 0 +5 address decode d0-d15 r/ w halt ds irq 16-bit mpu note: all other inputs not shown in this diagram should be connected to gnd.
MT9080B cmos 2-112 figure 16 - 1024 channel switch timing ck fp #2 internal counter (read address) data output d0o-d15o d a t a memor y timing data output d0o-d15o fp #1 internal counter (write address) data in d0i-d15i connection memor y timing -a? 1023 0 1 2 3 4 5 1022 1023 0 1 2 3 4 1021 1022 1023 0 1 2 3 1021 1022 1023 0 1 2 1021 1022 1023 0 1 2 addresses smx #1 data input/output frame boundary note 1: address is latched into the data memory by the first positive clock edge in a timeslot (edge for ch. 0). data will be clocked out by the first positive clock edge in the next timeslot (edge - for ch. 0). note 2: data is latched into the data memory by the first rising edge in a timeslot (edge a for ch. 0) and is written into the memory location addressed by the internal counter with the next rising edge (edge ? for ch. 0). addresses ahead of time; i.e., one channel before the addressed data is clocked out of the data memory. it may be necessary to provide an external bus enable one channel ahead of time in applications where precharging of the external data bus is required. in other applications where no precharge is required, control bit from the next channel may be used in order to ensure that the external bus is enabled at the same time as the channel is being clocked out of the device. the change detect ( cd) output of the connection memory is used to interrupt the mpu. as mentioned in the pin and functional descriptions, cd goes low when the internal crc performed by the device indicates a change in memory contents. this feature is particularly useful in switching applications where the connection memory is con?gured once and is not modi?ed for long periods of time, e.g., in network digital access crossconnect systems. any inadvertent corruption of the memory contents will cause cd to interrupt the processor. figure 17 - mapping of address and control signals onto connect memory data bits d15 - d14 unused d13 external driver enable d12 dm-1 or dm-2 select d11 message enable d10 ode control d9 - d0 source channel address
cmos MT9080B 2-113 switching any input channel to an output channel timeslot is possible by merely writing the address of the input channel in the connection memory location corresponding to the output channel timeslot. for example, to switch channel 1 to output channel 5 and enable output drivers during channel 5, the connection memory location corresponding to channel 5 should be loaded with hex 2001. this word will be clocked out of the connection memory during timeslot 4 and will cause the data memory to clock out contents of the memory corresponding to channel 1 during the channel 5 timeslot. the 16 bit word clocked out by the connection memory will also enable data memory output drivers, and, external drivers. 2048 channel switch matrix a 2048 channel, double buffered timeslot interchange switch can be constructed with three smxs as shown in figure 18. smx#1 and smx#2 are used to store data and switch it in time, while the third smx functions as a connection memory. smx#1 and 2 are operated in the counter mode and external mode alternatively in consecutive frames. in any speci?c frame, one of the two is in counter mode while the other is in external mode. the functions are reversed in the successive frame. the smx in counter mode is programmed to write data figure 18 - 2048 channel timeslot interchange circuit cm-2 smx #3 d11 d0o-d10o ode mz my mx fp ck +5 c16 mpu interface connection memory u2 u1 11 11 +5 16 16 16 c16 +5 c16 c16 16 d0-d15i ck fp mz r/ w ode a0-a10 me d0-d15o mx my cs ds cnt/ext smx #1 d0-d15i ck fp mz r/ w ode a0-a10 me d0-d15o mx my cs ds cnt/ext smx #2 data output data memory data memory timing generator dfp cfp 16.384 mhz notes: 1) u1 and u2 are required if the data output bus is to be enabled/disabled via the microprocessor interface. 2) all inputs not shown should be connected to ground (v ss ). dta ds r/ w cs a0-a15 cd d0-d15
MT9080B cmos 2-114 figure 19 - 2048 channel switch timing figure 20 - extended switching matrix ck dfp dfp (smx #2) data in (smx1/2) cfp (smx #3) smx #3 int. counter smx #3 d0o-d10o data out (smx 1/2) (smx #1) 2044 2045 2046 2047 0 1 2 2044 2045 2046 2047 01 2 2045 2046 2047 0 1 2045 2046 2047 01 2 2045 2046 2047 012 2045 2046 2047 01 2046 2047 2046 2047 0 1 2 written to smx #2 written to smx #1 read from smx #1 read from smx #2 written from smx #2 data in data in large matrix 1 dm dm cm ode ch 2,049-4,096 ch 1-2,048 ch 2,049-4,096 ch 1-2,048 large matrix 3 ode large matrix 2 ode large matrix 4 ode data out data out
cmos MT9080B 2-115 into its memories addressed by the internal counter. the smx in the external mode reads data out from memory locations addressed by the connection memory. in this manner, incoming data is continually written into one memory block while it is being read out of the other block. the device in counter mode has its output drivers disabled. this con?guration results in a maximum throughput delay of two frames. data clocked into the device in the current frame is clocked out in the next frame. the appropriate timing parameters are illustrated in figure 19. the clock signal applied to all three smxs has the same frequency. smx#3 is operated in connect memory mode-2. in this mode, data is clocked out of the device at the same rate as the clock, i.e., at 16.384 mbps. extended switching matrix larger extended switch matrices can be created using the 1024/2048 channel switch as a building block. as shown in figure 20, a 4096 channel matrix would require four smaller 2048 channel building blocks. construction of matrices larger than 4k may require external drivers to accommodate the greater capacitive loading on the outputs. using the smx for messaging in some system architectures the pcm voice signals and system status information is transmitted and received over a common backplane. to facilitate microprocessor access to the backplane, the smx can be used to read incoming data or write to a channel on the output data bus. data clocked into the smx can be read from the device by a microprocessor interfaced to the output data bus and the address bus (see figure 21). data can be written to a speci?c timeslot on the output data bus directly by the microprocessor using the messaging feature (enabled by tying the me pin high). a 1024 switch matrix with messaging capability can be constructed with three smxs as shown in figure 22. the ?rst smx is used for performing the actual switching function. the second smx is con?gured as the connection memory. as discussed in the 1024 switch application, by enabling the messaging feature, data clocked out of the connection memory and latched into the data memory address bus will be clocked out on to the data bus directly. incoming data is read by the microprocessor using the third figure 21 - reading the data memory with a microprocessor smx. the data output bus of the third smx is connected to the data bus of the mpu. figure 22 - a 1024 channel switch matrix with message capability ck fp d0-d15i z y x cs a0-a11 ds dta cd r/ w d0-d15o ode address ds halt irq d0-d15 m p u address decode 16 16 +5v +5v dm-1/dm-2 smx #1 data memory smx #2 connection memory smx #3 messaging dm-1/2 dm-1 cm-1/2 mpu data in data out 16 16 addr me +5v 16 d0 i - d15 i addr d0 o - d15 o addr data addr data 16 16
MT9080B cmos 2-116 parallel-to-serial conversion the smx can be used in systems which employ serial architectures by converting the parallel i/o into a serial format. the mitel mt9085 parallel access circuit (pac) is designed to interface to the parallel busses of the smx. a single pac can convert the output of a1024 channel switch into 2.048 mbit/s or 4.096 mbit/s serial format. a second pac can be con?gured to implement serial to parallel conversion (see figure 23). the pac generates all framing signals required to implement a 1024 or 2048 channel matrix. refer to the mt9085 data sheet for more information on operation of the pac. for more information, see mitels application note msan-135 design of large digital switching matrices using the smx/pac . figure 23 - 1024 channel serial switch matrix using the pac and smx timing source c4i c16i s0 s31 ? ? ? ? 2/4s oe ckd mca mcb p0-p7 dfpo cfpo pac s/p f0i ? ? ? ? s0 s31 c16 c4 f0 8 c16 +5 +5 d0-d7i ck fp mz r/ w ode a0-a9 me d0-d7o mx my cs ds 8 smx #1 dm - 1/2 f0 c4 c16 f0i c4i c16i p0-p7 oe ckd mca mcb 2/4s +5 ? ? ? ? s0 s31 ? ? ? ? s0 s31 pac p/s smx #2 cm - 1 d12 d0-d9 d11 d10 ode mx my mz fp ck +5 +5 c16 mpu interface note: connect all inputs not shown to v ss 10 connection memory data memory dta ds r/ w cs a0-a15 cd d0-d15
cmos MT9080B 2-117 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings* parameter symbol min max units 1 supply voltage v dd -v ss v dd -0.3 7 v 2 all input voltages v i v ss -0.3 v dd +0.3 v 3 all output voltages v o v ss -0.3 v dd +0.3 v 4 storage temperature range t s -40 125 c 5 current at digital outputs i o 150 ma 6 continuous power dissipation p d 2w recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 supply voltage v dd 4.75 5.0 5.75 v 2 operating temperature t op -40 70 c 3 input high voltage v ih 0.7v dd v 4 input low voltage v il 0 0. 3v dd v dc electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 supply current i dd 120 200 ma outputs unloaded 2 input high voltage v ih 0.7v dd v 3 input low voltage v il 0 0.3v dd v 4 input leakage current i il 10 m a 5 output high current (all outputs except d0i-d15i) i oh 8mav oh =0.7 v dd 6 output low current (all outputs except dt a, cd and d0i-d15i) i ol 8mav ol =0.3 v dd 7 output high current d0i-d15i i oh 2mav oh =0.7 v dd 8 output low current dt a & cd i ol 2mav ol =0.3 v dd 9 input capacitance c i 10 pf 10 output pin capacitance c o 10 pf v dd =5.0v 10%. 11 high impedance leakage i oz 10 m a
MT9080B cmos 2-118 ? timing is over recommended temperature and power supply voltages. ? typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 24 - output drive enable timing ac electrical characteristics ? - output drive enable timing (see fig. 24) - voltages are with respect to ground (v ss ) unless otherwise stated . characteristics sym min typ ? max units test conditions 1 ode setup t os 0ns 2 ode hold t oh 20 ns 3 data output high z to active t dza 35 ns c l =30pf 4 data output active to high z t daz 30 ns 1. data memory modes and connect memory mode - 1 2. counter, external and connect memory mode - 2 ck ode d0o- d15o ck ode d0o- d15o high impedance state - output drivers disabled channel n channel n + 1 t os t oh t os t oh t dza 90% 10% t daz channel channel n n + 2 channel n + 1 t os t oh t os t oh t os t oh t dza t daz 90% 10%
cmos MT9080B 2-119 ? timing is over recommended temperature and power supply voltages. ? typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 25 - data memory, connect memory-1 and shift register mode timing ? timing is over recommended temperature and power supply voltages. ? typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. ac electrical characteristics ? - data memory, connect memory-1 and shift register mode timing (see fig. 25) - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 address setup t as 0ns 2 address hold t ah 18 ns 3 data output delay t dd 934nsc l = 30 pf 4 data input setup t ds 2ns 5 data input hold t dh 4ns 6 me, mx, my, mz setup t mes 0ns 7 me, mx, my, mz hold t meh 26 ns 8 ck clock period t pck 60 ns ac electrical characteristics ? - external, connect memory-2 and counter mode timing (see fig. 26) - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 addr, r/ w hold time t weh 10 ns 2 addr,r/ w setup time t wes 2ns 3 data setup t ds 2ns 4 data hold t dh 4ns 5 data output delay t dd 934nsc l = 30 pf 6 me, mx, my, mz setup t mes 0ns 7 me, mx, my, mz hold t meh 26 ns ck a0-a15* me/mx/y/z d0o-d15o d0i-d15i* t as t dh t ds t dh t ah t ah t as t mes t meh t as t meh t mes t dd t dd t ds t pck channel timeslot *timing applicable to data memory and shift register modes only.
MT9080B cmos 2-120 figure 26 - external, connect memory-2 and counter mode timing ? timing is over recommended temperature and power supply voltages. ? typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 27 - address bus timing in shift register mode ac electrical characteristics ? - address bus timing in shift register mode (see fig. 27) - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 address setup t as 0ns 2 address hold t ah 12 ns 3 chip select setup t css 0ns 4 chip select hold t csh 0ns ck a0-a15*, r/ w ** me/mx/y/z d0i-d15i** d0o-d15o * ** timing applicable to external mode only. timing applicable to external and counter modes. t wes t weh t wes t mes t mes t meh t meh t ds t dh t ds t dh t dd t dd t weh channel timeslot cs ds a0-a15 t csh t css t as t ah
cmos MT9080B 2-121 *t ck = clock (ck) period ? timing is over recommended temperature and power supply voltages. ? typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 28 - microprocessor read timing for connect memory mode, data memory mode and external mode ac electrical characteristics ? - microprocessor read timing for connect memory, data memory & external modes (see fig. 28) - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 chip select setup t css 0ns 2 chip select hold t csh 0ns 3 addr t as 0ns 4r/ w setup t as 3ns 5 addr, r/ w hold t ah 0ns 6 dt a delay t dtad 4.5 9 t ck * 7 dt a hold t dtah 0ns 8 valid data out to dta low t rd 3t ck * 9 ds high to data invalid t dh 027ns 10 output data active to high z t dhz 31 ns ds cs a0-a15, r/ w dt a data bus* t css t csh t as t ah t dtad t dtah t rd t dhz t dh * in data memory mode and external mode, data is clocked out on d0o-d15o; in connect memory mode data is clocked out on d0i-d15i (bidirectional).
MT9080B cmos 2-122 *t ck = clock (ck) period ? timing is over recommended temperature and power supply voltages. ? typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 29 - microprocessor write timing for connect memory mode ac electrical characteristics ? - microprocessor write timing for connect memory mode (see fig. 29) - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 chip select setup t css 0ns 2 chip select hold t csh 0ns 3 addr, r/ w setup t as 0ns 4 addr, r/ w hold t ah 0ns 5 dt a delay t dtad 4.5 7.5 t ck * 6 dt a hold t dtah 0ns 7 ds low to data in delay t dd 4.5 t ck * 8 dt a low to data in hold t dh 0ns 9 ds hold time t dsh 0ns ds cs a0-a15,r/ w dt a d0-d15i t css t as t dsh t csh t ah t dtad t dh t dtah* t dd * this parameter is specified with respect to the rising edge of ds or cs depending on which signal goes high first.
cmos MT9080B 2-123 ? timing is over recommended temperature and power supply voltages. ? typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 30 - frame pulse and change detect timing ac electrical characteristics ? - frame pulse, clock and change detect timing (see fig. 30) - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 frame pulse setup t fps 6ns 2 frame pulse hold t fph 3ns 3 change detect delay t cdd 38 ns 4 change detect reset delay t cdrd 013ns ck fp ds / cs cd t fps t fph t cdd* t cdrd * assumes change in memory contents detected in previous frame
package outlines plastic j-lead chip carrier - p-suf?x f d 1 d h e 1 i a 1 a g d 2 e e 2 dim 20-pin 28-pin 44-pin 68-pin 84-pin min max min max min max min max min max a 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.200 (5.08) 0.165 (4.20) 0.200 (5.08) a 1 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.130 (3.30) 0.090 (2.29) 0.130 (3.30) d/e 0.385 (9.78) 0.395 (10.03) 0.485 (12.32) 0.495 (12.57) 0.685 (17.40) 0.695 (17.65) 0.985 (25.02) 0.995 (25.27) 1.185 (30.10) 1.195 (30.35) d 1 /e 1 0.350 (8.890) 0.356 (9.042) 0.450 (11.430) 0.456 (11.582) 0.650 (16.510) 0.656 (16.662) 0.950 (24.130) 0.958 (24.333) 1.150 (29.210) 1.158 (29.413) d 2 /e 2 0.290 (7.37) 0.330 (8.38) 0.390 (9.91) 0.430 (10.92) 0.590 (14.99) 0.630 (16.00) 0.890 (22.61) 0.930 (23.62) 1.090 (27.69) 1.130 (28.70) e 0 0.004 0 0.004 0 0.004 0 0.004 0 0.004 f 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) g 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) h 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) i 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) for d & e add for allowable mold protrusion 0.010" e: (lead coplanarity) general-10
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.

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